Mixed mode transceiver digital control network and collision-free communication method

ABSTRACT

A mixed mode transceiver digital control network system is disclosed as including at least two nodes/transceivers connected with a DC power source and a cored inductor via a bus, in which each transceiver includes a current mode transmitter and a voltage mode receiver. A bi-directional voltage clamp is connected in parallel to the cored inductor. Electric current from the DC power source flows through the cored inductor and the bi-directional clamp into the bus. By reason of the flow of the electric current through the voltage clamp, a electric voltage pulse is generated and transmitted into the bus. The electric voltage pulse so transmitted into the bus is received by the voltage mode receiver and subsequently inputted into a micro-controller or processor of the node. There is also disclosed a method of setting one of a plurality of priority levels to each node forming the system, so that a node to which a higher priority level has a higher chance of transmitting its data packets. There is further disclosed a method of avoiding collision when two or more nodes/transceivers transmit their respective data packets at the same time.

[0001] This invention relates, in general, to the field of wired digitalcontrol network systems. In particular, this invention relates to awired communication and control network system and a method for avoidingcollision in the transmission of data in such a system.

BACKGROUND OF THE INVENTION

[0002] Home and building automation is an important area in thedevelopment of modem technology, of which the design of control systemsis one of its crucial areas. Many proposals have been put forward inthis field, e.g. “X-10”, “Lonwork”, “CEBus” and “EIB”.

[0003] Home and building control systems are complicated andmulti-faceted systems. Stand-alone or point-to-point products clearlycannot fulfill the various requirements which may arise in real lifesituation. A control network system is much more versatile and maytherefore meet such requirements. The nodes in such a control networksystem can communicate with one another, share the same resources, andbe assembled together by various means (e.g. switches, sensors, timers,telephones, computers, etc.) in the light of the needs, in order torealize various control functions, e.g. integrated control andmonitoring of lighting, energy, access and security at home or office.

[0004] Centralized control system is a well-known technology. However,the application of such a technology in home and building automation hasmet with various problems, e.g. complicated wiring (due to the largenumber of wires required), difficulty in extending the system (as thereis usually a fixed capacity for each central control system), spacerequirement (due to the need to accommodate the central unit usually ina separate room), and the rigorous requirements for reliability (e.g.the whole system will not function when there are problems with thecentral unit).

[0005] At present, there are many media access control (MAC) methods,e.g. token passing, polling, circuit switching, and time-divisionmultiple access (TDMA), etc. However, to a control network, while thesignals/data to be transmitted are usually relatively short, theresponse speed is required to be relatively high. Random access is thusone of the few methods which can meet the requirements of a real-timecontrol.

[0006] In a random access system, it is possible that more than one nodeseek to transmit signals/data at the same time, resulting in acollision. Various methods have been devised to resolve suchcontentions, to recover from collisions, or to avoid collisions. Suchmethods include CSMA/CD (Carry Sense Multiple Access with CollisionDetection) and CSMA/CA (Carry Sense Multiple Access with CollisionAvoidance). However, irrespective of the method used, if two or morenodes transmit signals/data at the same time, all such attemptedtransmissions will fail. Each of these nodes has to stop transmittingfor a respective period of time, and tries transmitting again. Such willcause a reduction of the communication efficiency.

[0007] Most current communication networks do not consider tie issue ofpriority. If the data packets to be transmitted are not queuedsequentially, each has to wait for the same pre-determined period oftime before it is transmitted. This is a conventional method for, anddoes not cause much difficulty to, a communication system. However, theissue of priority becomes very important to a control system. Thedifference could be very significant since different nodes may carry outdifferent functions within the system. In case of emergency, seriousproblems may arise if certain important signals/data cannot betransmitted by a particular node.

[0008] To a wired control network, it is desirable to keep the number ofwires to a minimum. The more are the number of wires, the moreinconvenient the wiring process will be, and the higher the risk ofmis-wiring will also be. For example, even in a network in which thereare only four wires (e.g. USB), there are 23 (i.e. (4!-1)) ways ofmis-wiring.

[0009] While it is a common practice to provide a separate power sourcefor each node in the network, it is desirable to provide electric powerto the nodes through the network. Common link power systems generallyadopt transformer coupling to separate power from signals in thebus/transmission medium. Because of the use of transformers, the systemis usually of a relatively large size, and thus more expensive. Inaddition, due to the relatively low internal resistance of thetransformer, the fanning-out capacity of the bus/transmission mediumwill be lowered when the transformer is connected to the network.

[0010] It is thus an object of the present invention to provide, a mixedmode transceiver digital control network system, a transceiver, a methodof setting priority to each node, and a method for avoiding collision insuch a system, in which the aforesaid shortcomings are mitigated, or atleast to provide a useful alternative to the public.

SUMMARY OF THE INVENTION

[0011] According to a first aspect of the present invention, there isprovided a digital data communication network system including a powersupply means and at least two nodes, wherein said power supply means andsaid nodes are connected to one another via a transmission media wherebydigital signals/data are transmissible between said nodes, wherein saidpower supply means supplies electric power to said nodes, and wherein atleast one of said nodes includes a current mode transmitter and at leastone of said nodes includes a voltage mode receiver.

[0012] According to a second aspect of the present invention, there isprovided a digital data communication system for delivering digitalsignals from a current mode transmitter to a voltage mode receiver, saidsystem including an electrically conductive cable coupling saidtransmitter and said receiver with each other, thereby providing adigital data communications path; DC power supply means for producing apre-determined electric potential, said power supply means having afirst voltage terminal and a second voltage terminal; current controlmeans coupling said first voltage terminal of said power supply means tosaid cable for providing a first electric current path, said firstelectric current path operating as a low impedance path for DC current;voltage control means connected in parallel with said current controlmeans for controlling the voltage amplitude across said current controlmeans, and for providing a second electrical path for transient electriccurrent; connecting means coupling said second voltage terminal of saidpower supply means to said cable to provide a power distribution path;wherein said current mode transmitter is coupled to said cable forimplementing a current loop, wherein said transmitter produces currentpulses in said current loop to perform a current mode digital datatransmission; and wherein said voltage mode receiver is coupled to saidcable for receiving voltage pulses on said cable produced by saidvoltage control means to perform a voltage mode digital data reception.

[0013] According to a third aspect of the present invention, there isprovided a digital data communication network system for distributingpower and for providing signal passing capabilities through a bus, saidnetwork including a plurality of nodes each including a mixed mode databus transceiver for generating electric current pulses and receivingelectric voltage pulses; an electrically conductive cable coupling saidnodes with one another to provide a path for power delivery and datacommunications; a DC power supply means for producing a pre-determinedelectric potential, said power supply means having a first voltageterminal and a second voltage terminal; current control means couplingsaid first voltage terminal of said power supply means to said cable forproviding a first DC current low impedance path; voltage control meansconnected in parallel with said current control means for controllingthe voltage amplitude across said current control means and providing asecond current path for transient current; and connection means couplingsaid second voltage terminal of said power supply means to saidconductive cable to provide a power distribution path.

[0014] According to a fourth aspect of the present invention, there isprovided a transceiver adapted to transmit and receive digital signalson a data bus which delivers direct current power and digital datasimultaneously, said transceiver including a bridge rectifier having twoconnection terminals adapted to provide a non-polarity interface withsaid bus, said rectifier further including a +terminal and a −terminal;a current mode transmitter coupled to said +terminal and said −terminalof said rectifier for implementing a current loop adapted to produceelectric current pulses to said data bus to perform current mode datatransmission; a voltage mode receiver coupled to said +terminal and said−terminal of said rectifier, said receiver being adapted to receiveelectric voltage pulses on said data bus to perform voltage mode datareception; and a current coupling means coupled to said +terminal andsaid −terminal of said rectifier, said current coupling means beingadapted to provide a regulated direct current supply to said transmitterand said receiver and other means in said transceiver.

[0015] According to a fifth aspect of the present invention, there isprovided a method of communication in a mixed mode communication andcontrol network system, wherein said system includes at least a firstnode, a second node, a power supply means, and current to. voltageconverter means connected with one another via a bus, comprising thesteps of (a) generating at least a first electric pulse by said firstnode; (b) transmitting said first electric pulse to said power supplymeans in the form of an electric current; (c) causing a first electriccurrent from said power supply means to pass through said current tovoltage converter means to induce at least a second electric pulse; and(d) transmitting said second electric pulse into said bus.

[0016] According to a sixth aspect of the present invention, there isprovided a method for medium access control in a mixed modecommunication and control network system, wherein said system includesat least a first node and a second node each being adapted to transmitsignals into a bus via which said nodes are connected with each other,including the steps of (a) establishing a plurality of priority levelseach with a corresponding different range of waiting time; (b) assigningone of said plurality of priority levels to each of said nodes; (c) saidfirst node generating a waiting time on the basis of the priority levelassigned thereto; (d) said first node checking whether said bus is freefor transmission; (e) said first node checking whether the said waitingtime has expired; (f) repeating steps (d) and (e) until the waiting timehas expired; and (g) commencing transmission of a first data packet bysaid first node if said bus is free for transmission.

[0017] According to a seventh aspect of the present invention, there isprovided a method of transmitting data in a mixed mode communication andcontrol network system, wherein said system includes at least a firstnode and a second node each being adapted to transmit pulses into a busvia which said nodes are connected with each other, including the stepsof (a) said first node causing a pulse of a first polarity. to betransmitted into said bus; (b) said first node checking whether a pulseof said first polarity appears on said bus; and (c) finishing sendingsaid pulse of said first polarity into said bus for the full period ofpulse time-width if a pulse of said first polarity is detected on saidbus in step (b).

[0018] According to an eighth aspect of the present invention, there isprovided a method of transmitting at least one data packet for providinga collision-free communications in a mixed-mode multi-drop random accessdigital control network, wherein said network includes at least a firstnode and a second node each being adapted to transmit and receive datapackets through a bus via which said nodes are connected with each otherand constituting a wired-AND logic, wherein said data packet includes atleast a logic high and a logic low to be transmitted into said bus, saidmethod including the steps of:

[0019] (a) when said first node seeks to transmit said logic low intosaid bus, said first node;

[0020] (1) checks logic state from said bus;

[0021] (2) starts to transmit said logic low into said bus if said buspresents logic high in step (1) above;

[0022] (3) completes transmitting said logic low into said bus for thefull period of the time-width of the said logic low; and

[0023] (b) when said first node seeks to transmit said logic high intosaid bus, said first node:

[0024] (1) starts to transmit said logic high into said bus;

[0025] (2) checks logic state from said bus;

[0026] (3) checks whether a pre-determined waiting time is up; and

[0027] (4) repeats steps (b)(2) and (b)(3) until said first nodecompletes transmission of said logic high into said bus for the fullperiod of the time-width of said logic high if said bus keep onpresenting logic high in step (b)(2).

[0028] According to a ninth aspect of the present invention, there isprovided a method of transmitting at least one data packet for providinga collision-free communications in a mixed-mode multi-drop random accessdigital control network, wherein said network includes at least a firstnode and a second node each being adapted to transmit and receive datapackets through a bus via which said nodes are connected with each otherand constituting a wired-OR logic, wherein said data packet includes atleast a logic high and a logic low to be transmitted into said bus, saidmethod including the steps of.

[0029] (a) when said first node seeks to transmit said logic high intosaid bus, said first node:

[0030] (1) checks logic state from said bus;

[0031] (2) starts to transmit said logic high into said bus if said buspresents logic low in step (1) above;

[0032] (3) completes transmitting said logic high into said bus for thefall period of the time-width of the said logic high; and

[0033] (b) when said first node seeks to transmit said logic low intosaid bus, said first node:

[0034] (1) starts to transmit said logic low into said bus;

[0035] (2) checks logic state from said bus;

[0036] (3) checks whether a pre-determined waiting time is up; and

[0037] (4) repeats steps (b)(2) and (b)(3) until said first nodecompletes transmission of said logic low into said bus for the fullperiod of the time-width of said logic low if said bus keep onpresenting logic low in step (b)(2).

[0038] According to a tenth aspect of the present invention, there isprovided a transceiver adapted to transmit and receive digitalsignals/data via a mixed mode bus which delivers direct current powerand digital data simultaneously, said transceiver including current modetransmitter means for implementing a current loop adapted to produceelectric current pulses to said bus to perform a current mode datatransmission, and voltage mode receiver means for receiving electricvoltage pulses on said bus to perform voltage mode data reception.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Preferred embodiments of the invention will now be described byway of examples, and with reference to the accompanying drawings, inwhich:

[0040]FIG. 1 is a schematic diagram of a conventional voltage modemulti-drop network system;

[0041]FIG. 2 is a schematic diagram of a conventional current modemulti-drop network system;

[0042]FIG. 3 is a schematic diagram of a first mixed mode multi-dropnetwork system according to the present invention;

[0043]FIG. 4 is a schematic block diagram of a first embodiment of anapplication system according to the present invention;

[0044]FIG. 5 is a schematic block diagram of a second embodiment of anapplication system according to the present invention;

[0045]FIG. 6 shows the current flow and the voltage change at certainpoints of the system when a negative pulse is transmitted into the busand received by a receiver in the embodiment shown in FIG. 5;

[0046]FIG. 7 shows the current flow and the voltage change at certainpoints of the sytem when a positive pulse is transmitted into the busand received by a receiver, after a negative pulse has just beentransmitted into the bus in the embodiment shown in FIG. 5;

[0047]FIG. 8 shows the data frame format used in the system according tothe present invention;

[0048]FIG. 9 shows the data bits format used in the system according tothe present invention;

[0049]FIG. 10 shows the data packet format used in the system accordingto the present invention;

[0050]FIG. 11 is a table showing the respective waiting time of thepriority levels;

[0051]FIG. 12 is a flowchart showing the process whereby a node initialsa transmission;

[0052]FIG. 13 is a timing chart showing a method for access control andcollision avoidance according to the present invention;

[0053]FIGS. 14 and 15 are flowcharts showing the back-off method forcollision avoidance;

[0054]FIG. 16 is a schematic block diagram showing a four-node systemaccording to the present invention, in which the four nodes attempt totransmit signals/data simultaneously;

[0055]FIGS. 17A to 17D show the respective waveform of the voltage atthe output of the micro-controller of the four nodes in FIG. 16;

[0056]FIGS. 18A to 18D show the respective waveform of the sink currenti_(a), i_(b), i_(c), and i_(d) of the four nodes in FIG. 16;

[0057]FIGS. 19A to 19D show the respective waveform of the voltage atthe input of the micro-controller of the four nodes in FIG. 16;

[0058]FIG. 20 shows the waveform of the DC supply source current i ofthe system shown in FIG. 16;

[0059]FIG. 21 shows the waveform of the inductor source current i_(l) ofthe system shown in FIG. 16;

[0060]FIG. 22 shows the waveform of the current i_(p) flowing throughthe bi-directional clamp of the system shown in FIG. 16;

[0061]FIG. 23 shows the waveform of the voltage v_(p) across thebi-directional clamp of the system shown in FIG. 16;

[0062]FIG. 24 shows the waveform of the bus voltage v of the systemshown in FIG. 16; and

[0063]FIG. 25 is a schematic diagram of a second mixed mode multi-dropnetwork system according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0064] At present, the most common network system is “voltage modenetwork”. A schematic diagram of such a system is shown in FIG. 1; Ascan be seen in FIG. 1, a number of nodes/transceivers 10 (four as shownin FIG. 1) are connected to a bus 12 to form a voltage mode network 14.In each of the nodes/transceivers 10 is a voltage mode transmitter 16,and a voltage mode receiver 18. The transceivers 10 (e.g. EIA-485) ofsuch a system 14 operate by means of electric voltage. The digitalsignals/data transmitted through the transmission media (i.e. the bus12) are in the form of different levels (high or low) of electricvoltage. If a medium of a smaller nominal capacitance is chosen, and isused in conjunction with a receiver of a higher input impedance, thesystem will usually be of a higher fanning-out capacity. For example, anEIA-485 transceiver usually has a fanning-out capacity of 32. However, asmaller capacitance and a higher impedance will reduce theanti-interference capacity of the system. As a result, a voltage modenetwork, as compared with a current mode network (to be discussedbelow), is more easily interfered by outside electromagnetic field.

[0065] As to a “current mode network”, such usually refers to a currentmode/loop multi-drop system, a schematic diagram of which is shown inFIG. 2. As shown in FIG. 2, three nodes/current mode transceivers 20 areconnected with a current source 22 to form a system, via a closed-loopbus 24. Each of the transceivers 20 includes a current mode transmitter26 and a current mode receiver 28. In such a system, the transmitter(e.g. HCPL-4100 of Hewlett Packard) and receiver (e.g. HCPL-4200 ofHewlett Packard) operate by means of electric current. The digitalsignals/data transmitted in the transmission media are in the form ofelectric current of different magnitude (Mark/Space). As the receiver ofa current mode system has a low input impedance, such a system usuallyhas a higher anti-interference capacity. However, as all thetransceivers in such a network have to be linked up to form a closedloop, such will reduce the reliability of the system. In particular, ifthere is an open circuit at any point, the whole system will break down.The fanning-out capacity of such a transceiver is also smaller. Forexample, a current mode system can usually consist of severaltransceivers. Such a system is therefore only suitable for use in asimple yet high-interference setting.

[0066] A mixed mode multi-drop network system 100 according to thepresent invention is shown schematically in FIG. 3. As can be seen,three nodes/mixed mode transceivers 102 are connected with one anotherto form the system 100 via a bus 104 in the form of a single unshieldedtwisted pair (UTP) wire. Each node 102 includes a current modetransmitter 102 a and a voltage mode receiver 102 b. The transmitter 102a of the respective nodes 102 transmits signals/data via the bus 104 toother node(s) 102, and the receiver 102 b of the respective nodes 102receives signals/data from other node(s) 102 via the bus 104. It shouldbe noted that the digital signals/data transmitted by the transmitters102 a are in the form of electric current of different magnitude(Mark/Space). On the other hand, the digital signals/data received bythe receivers 102 b are in the form of different (high or low) levels ofelectric voltage.

[0067] Also connected with the nodes 102 via the bus 104 is a DC powersupply 106 and a converter 107, which acts as a pulse generator. Theconverter 107 includes a current controller 108 which provides anelectric current i(v_(p), t) to the system, in which the magnitude ofthe electric current i(v_(p), t) varies as a function of the electricvoltage v_(p) across the current controller 108 and the length of time tduring which the electric current flows through the current controller108. Connected in parallel with the current controller 108 is a voltagecontroller (also called a current to voltage converter) 110. Thisvoltage controller 110 ensures that the electric current from differenttransmitters 102 a will be converted into the same electric voltage fortransmission into the bus 104. Another function of the voltagecontroller 110 is to ensure that, when more than one transmitter 102 aare transmitting simultaneously, the electrical pulse level in the bus104 will not exceed a pre-determined range, e.g. 1.5V-3V.

[0068] A first embodiment of an application system according to thepresent invention is shown schematically in FIG. 4. This system 200includes a network power supply 202 electrically connected to two nodes204 a, 204 b. The network power supply 202 is electrically connectedwith the nodes 204 a, 204 b via a bus 206 (in the form of a singleunshielded twisted pair (UTP) wire).

[0069] The network power supply 202 includes a DC power source 208, anda converter (which acts as a pulse generator) comprising a currentcontroller in the form of a cored inductor 210 and a voltagecontroller/current to voltage converter in the form of a bi-directionalvoltage clamp 212. In this example, the voltage clamp 212 includes twopairs of diodes 214 a, 214 b arranged in parallel but oppositedirections. The output from the DC power source 208 passes through theinductor 210 before it is transmitted to the bus 206.

[0070] The node 204 a includes a current mode transmitter 216 (includinga transistor 218 and a resistor 220), a current coupling circuit 228 anda bridge rectifier 230. The current coupling circuit 228 directlycouples the DC current in the bus 206 while not affecting the digitalsignals in the bus 206. The node 204 a is also connected to anapplication module 221 including a micro-controller or processor 222connected to a sensor 224. In this embodiment, the sensor 224 is in theform of a switch. The transistor 218 is connected to the output port(O/P) of the micro-controller or processor 222 (e.g. INTEL 80C51series), which controls the operation of the current mode transmitter216. The current coupling circuit 228 includes a zener diode 229 forproviding a regulated and stable direct power source to the node 204 a.The V_(DD) of the micro-controller or processor 222 is also connected tothe current coupling circuit 228 whereby the micro-controller orprocessor 222 is also powered by the same DC power source 208 of thesystem.

[0071] As to the node 204 b, such includes a voltage mode receiver 226,a current coupling circuit 234 and a bridge rectifier 232. As in thecase of the current coupling circuit 228 in the node 204 a, the currentcoupling circuit 234 in the node 204 b directly couples the DC currentin the bus 206 while not affecting the digital signals in the bus 206.As to the voltage mode receiver 226, such includes a capacitor 236 andan inverter circuit (including resistors 238 a, 238 b, 238 c and atransistor 240). The transistor 240 is connected to the input port (I/P)of a micro-controller or processor 242 of an application module 243 forinputting the electric pulses received from the bus 206 into themicro-controller or processor 242. Upon receipt of such electric pulses,the micro-controller or processor 242 may then, according to apre-determined procedure, give out a signal to a control module 244 toperform certain control functions. In this embodiment, the controlmodule 244 includes a light bulb 246 which will be turned on whencertain pre-determined electric pulses are received by themicro-controller or processor 242. The current coupling circuit 234includes a zener diode 235 for providing a regulated and stable directpower source to the receiver 226. The V_(DD) of the micro-controller orprocessor 242 is also connected to the current coupling circuit 234whereby the micro-controller or processor 242 is also powered by thesame DC power source 208 of the system.

[0072] It can be seen that a complete communication and control processcan be performed by the system 200 in which when the switch constitutingthe sensor 224 in the application module 221 is closed, electric pulsesare caused by the current mode transmitter 216 to be transmitted intothe bus 206. Such electric pulses are received by the voltage modereceiver 226 of the node 204 b and inputted into the micro-controller orprocessor 242 to output a signal, which is in the form of the lightingup of the bulb 246 in the present embodiment. Electric power is alsodelivered from the DC power source 208 to the various nodes 204 a, 204 band application modules 221, 243 of the system 200. In particular, itcan be seen that no transformer is required in this system.

[0073] It can also be seen that, because of the existence of the bridgerectifiers 230, 232 in the respective nodes 204 a, 204 b, no mis-wiringwill occur in the system 200. Take the node 204 b as an example.According to the present connection, the electric current from the DCpower source 208 will flow (in the convention manner) into the node 204b via diode 250 a, and return via diode 250 b. Even if a “mis-wiring”occurs (as shown by the dotted lines in FIG. 4), the electric currentfrom the DC power source 208 will flow into the node 204 b via diode 250c, and returns via diode 250 d. Such therefore ensures that thedirection of the flow of the electric current in the node 204 b and theapplication module 243 is the same irrespective of the way in which thewires of the node 204 b are connected to the bus 206.

[0074] It can also be seen that, as shown in FIG. 4, the bridgerectifier 230 include two terminals coupled to the bus 206 for providinga non-polarity interface with the bus 206, in which the bridge rectifier230 includes a +terminal and a −terminal. The current coupling circuit228 includes a constant current source 231 with two terminals, one ofwhich being connected to the +terminal of the bridge rectifier 230.Another end of the constant current source 231 is connected to the−terminal of the bridge rectifier 230 via the zener diode 229. By way ofsuch an arrangement, electric power is supplied to the applicationmodule 221.

[0075] The transmitter 216 also includes the transistor 218, whichincludes a collector coupled to the +terminal of the bridge rectifier230, a base for transmitting data to be transmitted into the transistor218, and an emitter. The resistor 220 is coupled at one end to theemitter of the transistor 218 and at another end to the −terminal of thebridge rectifier 230, so as to implement a transmission output currentloop.

[0076] The bridge rectifier 232 includes two terminals coupled to thebus 206 for providing a non-polarity interface with the bus 206, inwhich the bridge rectifier 232 includes a +terminal and a −terminal. Thecurrent coupling circuit 234 includes a constant current source 237 withtwo terminals, one of which being connected to the +terminal of thebridge rectifier 232. Another end of the constant current source 237 isconnected to the −terminal of the bridge rectifier 232 via the zenerdiode 235. By way of such an arrangement, electric power is supplied tothe receiver 226. The receiver 226 includes the capacitor 236 coupled tothe +terminal of the bridge rectifier 232 for isolating the directcurrent potential on the +terminal of the bridge rectifier 232.

[0077] A second embodiment of an application system according to thepresent invention is shown schematically in FIG. 5. This system 300 isvery similar to the system 200 shown in FIG. 4. One of the majordifferences is that both nodes 302 a, 302 b include a current modetransmitter 304 and a voltage mode receiver 306, so that each of thenodes 302 a, 302 b is a transceiver capable of both transmitting signalsand receiving signals via a bus 308. Inter-communication is thereforepossible between these two nodes 302 a, 302 b. As the structure of bothnodes 302 a, 302 b and their connection with the rest of the system 300are the same, we shall only discuss the node 302 a in more detail.

[0078] As shown in FIG. 5, a transistor 309 of the current modetransmitter 304 is connected to the output port (O/P) of amicro-controller or processor 310, while the input port (I/P) of themicro-controller or processor 310 is connected to a transistor 312 ofthe voltage mode receiver 306. By way of such an arrangement, themicro-controller or processor 310 can control the transmission ofsignals/data into the bus 308 via the current mode transmitter 304, andcan receive signals/data from the bus 308 via the voltage mode receiver306. The micro-controller or processor 310 is also connected to a sensor314 and a control module 316, the operation and functions of which areas discussed above. A two-way digital data network system for sensing,communication and control is thus realized. The micro-controller orprocessor 310 is also connected to a priority setting module 318, thefunction of which will be discussed below.

[0079]FIG. 6 shows the current flow and the voltage change at certainpoints in the system 300 when a negative pulse is transmitted into thebus 308 and received by a receiver. Before proceeding with thisanalysis, we first consider the idle situation in which no node istransmitting any data/signals into the bus 308. In this situation, thetransistor 309 in the current mode transmitter 304 of the node is cutoff. The transmitter voltage (v_(t)) and the voltage at the O/P of themicro-controller or processor 310 is low. The receiver voltage (v_(r))and the voltage at the I/P of the micro-controller or processor 310 isalso low. The bus voltage is V₀, and the bus idle current is I₀.

[0080] When the sensor 314 is actioned upon (e.g. a switch is closed),the micro-controller or processor 310 of the node 302 senses this stateand outputs one or more predetermined data packets with a series ofpositive and negative pulses. If a negative electric pulse of atime-width T of τ is to be transmitted into the bus 308, themicro-controller or processor 310 will output a positive pulse of atime-width T of τ. When this electric pulse is received by thetransistor 309 of the transmitter 304, the transistor 309 starts toconduct and a sink current of I_(t) is induced and transmitted towards aDC power supply source 320 via the bus 308. As this system constitutes aclosed current loop, the electric current flowing therein would increaseinstantly from I₀ to I₀+I_(t). (In fact I₀ should increase instantly toI₀+I_(t)−I_(r). However, since I_(r) is negligible, such is not takeninto account here.) An electric current of I₀+i(t) will then flowthrough a cored inductor 322, while an electric current of I_(t)−i(t)will flow through a bi-directional voltage clamp 324 in the samedirection as the current I₀+i(t). It can be seen that the combinedelectric current flowing away from the inductor 322 and thebi-directional voltage clamp 324 is I₀+I_(t). The component i(t) in bothof these electric currents varies in accordance with the time duringwhich the current I₀+i(t) passes through the inductor 322, namely, fromt=0 to t=τ. As the inductor 322 acts as a current controller whichprevents the sudden increase of the flow of electric current through it,during the time between t=0 and t=τ, I₀+i(t) is smaller than I₀+I_(t),so that the DC power supply 320 has to pass an additional electriccurrent of I_(t)−i(t) through the bi-directional voltage clamp 324,which also acts as a voltage controller/current to voltage converter, inorder to fulfill the current requirements of I₀+I_(t) of the currentloop of the system 300. Since an electric current flows through thebi-directional voltage clamp 324 in the same direction as the currentflowing through the inductor 322, a negative electric pulse (i.e.negative with reference to V₀) of a time-width T of τ is induced, whichnegative electric pulse is then transmitted into the bus 308 to bereceived by other nodes of the same system.

[0081] When a negative electric pulse of a time-width T of τ is receivedby the voltage mode receiver 306 of the node 302, a capacitor 326couples the negative electric pulse to a resistor 328, thus drawing anegligible electric current I_(r) which is less than one-thousandth ofthe current I_(t). This causes a transistor 330 to conduct and transmita positive electric pulse of a time-width T of τ to the micro-controlleror processor 310. In this respect, the resistor 328, a resistor 332, thetransistor 330 and a resistor 334 combine to act as an inverter wherebythe negative electric pulse of the time-width T of τ is inverted to apositive electric pulse of a time-width T of τ. This positive electricpulse is then inputted into the micro-controller or processor 310 viaits input port (I/P), thus completing a signal transmission andreception process.

[0082] Referring to FIG. 7, when a positive electric pulse of atime-width T of τ is to be transmitted into the bus 308 after a negativeelectric pulse of a time-width T of τ has just been transmitted into thebus 308 (as shown in FIG. 6 above), the transistor 309 does not conductin this instance, so that the current I_(t) is cut off and drops to 0A.The current passing through the node and the DC power source 320 willdrop instantly from I₀+I_(t) to I₀ (ignoring the negligible I_(r)). Onthe other hand, at the time of the cut off of I_(t), the current flowingthrough the inductor 322 is I₀+i(τ). As the current passing through theinductor 322 cannot change instantly, the surplus current of i(τ) willflow through the bi-directional clamp 324 in a direction opposite tothat of the current passing through the inductor 322, thus generating apositive pulse (i.e. positive with reference to V₀) on the bus 308. Thepositive pulse so generated causes the current passing through theinductor 322 to decrease in the manner of I₀+i(τ)−i(t), from t=0 (whenthe cut off occurs) until t=τ, when the current passing through theinductor 322 will fall to I₀. In this connection, t is the time duringwhich the current I₀ +i(τ)−i(t) passes through the inductor 322, namely,from t=0 to t=τ. The current passing through the bi-directional voltageclamp 324 will also decrease in the manner of i(τ)−i(t). When t=τ, noelectric current will pass through the bi-directional voltage clamp 324.In any event, from t=0 to t=τ, the total electric current flowing out ofthe inductor 322 and the bi-directional clamp 324 will be I₀. Due to thepassing of the electric current i(τ)−i(t) through the bi-directionalclamp 324 in a direction opposite to the flow of the currentI₀+i(τ)−i(t) through the inductor 322, a positive electric pulse of atime-width T of τ is induced and transmitted into the bus 308.

[0083] When a positive pulse of a time-width T of τ is received by thenode 302, such is coupled by the capacitor 326 to the resistor 328. Theresistors 328, 332, 334 and the transistor 330 combine to act as aninverter to invert the positive pulse to a negative pulse of equaltime-width, which is then inputted into the micro-controller orprocessor 310 via its input port (I/P), thus completing the transmissionand reception of a signal.

[0084] In FIGS. 6 and 7, while it appears that the node 302 seems totransmit the electric pulse back to itself, such is only a simplifiedway of showing a complete course of transmission and reception ofelectric pulses. In an actual system, a first node may only include acurrent mode transmitter, while a second node may only include a voltagemode receiver, so that an electric pulse can only be transmitted fromthe first node and received by the second node (as shown in FIG. 4herein). Preferably, as shown in FIG. 5, the system may include a numberof nodes each including a current mode transmitter and a voltage modereceiver, so that each node acts as a transceiver whereby electricpulses may be transmitted and received among the nodes/transceivers.

[0085] As can also be seen, the node 302 includes a bridge rectifier 336with two terminals for providing a non-polarity interface with the bus308. The bridge rectifier further includes a +terminal and a −terminal.The current mode transmitter 304 is coupled to the +terminal and the−terminal of the bridge rectifier 336 for implementing a current loopfor producing electric current pulses to the bus 308 to perform acurrent mode data transmission. The voltage mode receiver 306 is alsocoupled to the +terminal and the −terminal of the bridge rectifier 336for receiving voltage pulses on the bus 308 to perform a voltage modedata reception. The node 302 also includes a current coupling circuit307 (including a constant current source 305 and a zener diode 303)which is also coupled to the +terminal and the −terminal of the bridgerectifier 336 for providing a regulated direct current supply to thenode 302.

[0086] The current mode transmitter 304 includes the transistor 309 withits collector coupled to the +terminal of the bridge rectifier 336, itsbase for inputting data to be transmitted to the transistor 309, and itsemitter coupled to the −terminal of the bridge rectifier 336 via aresistor 338. The voltage mode receiver 306 includes the transistor 330with a base and a collector coupled to the −terminal of the bridgerectifier 336 through the resistor 334 for outputting the data receivedfrom the bus 308. The receiver 306 also includes the capacitor 326 whichcouples the base of the transistor 330 with the +terminal of the bridgerectifier 336 through the resistor 328 for providing an AC path to thebus 308.

[0087] The current coupling circuit 307 includes the constant currentsource 305 with two terminals, one of which being coupled to the+terminal of the bridge rectifier 336 for sourcing a constant current.Another terminal of the constant current source 305 is coupled to the−terminal of the bridge rectifier 336 via the zener diode 303 forproviding a regulated DC voltage source.

[0088] In a preferred embodiment of the above system, the workingvoltage of the zener diode 303 is about 5 volts, the potential of the DCpower supply source 320 is approximately 24 volts, and the range offrequency of the current and voltage pulses in the node 302 is 5-50 kHz.

[0089] While only the transmission and reception of a singlenegative/positive electric pulse is described above, it should of coursebe understood that, in the actual situation, data are transmitted andreceived in the form of data packets, each containing a number ofpositive and negative signals. In the preferred embodiment according tothe present invention, a positive pulse can only follow a negativepulse. For this reason, each byte commences with a negative start bit(to be discussed below).

[0090] For the purpose of the following discussion, it should beunderstood that a negative pulse on the bus/transmission medium isdefined as a logic low state, while a positive pulse on thebus/transmission medium is defined as a logic high state. Put anotherway, if a logic low is to be transmitted, a negative pulse has to betransmitted to the bus. If a logic high is to be transmitted, then apositive pulse has to be transmitted to the bus.

[0091] In accordance with the present invention, it is possible toassign different priority levels to different nodes in the system, sothat the node to which a higher priority is assigned has a higher chanceof transmitting its data/signals into the bus. Referring first to FIG.8, such shows the preferred data frame format used in this system. Thisis a “Manchester-like” data coding in which a pulse of a pre-determinedtime duration of T represents a data bit “1” (irrespective of whether itis a positive pulse or a negative pulse), while two opposite pulses eachof a time duration of T/2 combine to represent a data bit “0”(irrespective of whether the first pulse is negative or positive). Eachbyte includes eight data bits, a parity bit and a stop bit (of a timeduration of T). In the preferred embodiment of the present system, andas shown in FIG. 9, the time duration T is 100 μs, and T/2 is thus 50μs, so that the data transfer rate is 10,000 bits per second.

[0092] Turning to FIG. 10, such shows the data packet format adopted inthe present system. It can be seen that each data packet is separatedfrom the following one by a waiting/idle time (to be discussed below)and a start bit of the following data packet.

[0093] As mentioned above, the nodes in the present system can beassigned one of a plurality of priority levels. Such is usually carriedout when the system is set up via the priority setting module 318 (seeFIG. 5) of each node. For an example, and as shown in FIG. 11, sevenpriority levels (from the 1^(st) to the 7^(th)) are set up. Eachpriority level corresponds to a range of waiting/idle time separatingthe transmission of data packets by the node to which the priority levelis assigned. In the preferred embodiment according to FIG. 11, the totalwaiting time (in ms) equals to the sum of the basic waiting time (in ms)which is specific to each particular priority level (1^(st) to 7^(th))and a random waiting time (in ms) within the range of 0-1 ms.

[0094] For data packets transmitted by a node to which a 1^(st) classpriority level is assigned, the basic waiting time is the shortest,namely 1 ms. A random waiting time (between 0 ms to 1 ms) is thengenerated by the micro-controller or processor of the particular node.The actual total waiting time is thus between 1-2 ms. For data packetstransmitted by a node to which a 7^(th) class priority level isassigned, the waiting time is the longest, namely 7 ms. Again, a randomwaiting time between 0 ms to 1 ms is then generated by themicro-controller of the particular node. The actual total waiting timeis thus between 7-8 ms. As a node will only attempt to transmit datapackets when the bus is checked to be available for transmission (to bediscussed below), the node to which a 1^(st) class priority level isassigned will have a much higher chance of transmitting its data packetsthan the node to which a 7^(th) class priority level is assigned.

[0095] Although only seven priority levels are assigned in this example,a different number of priority levels can in fact be set up. Inaddition, more than one node may be assigned the same priority level.For example, in a certain system, two nodes may be assigned a 1^(st)class priority level, and three nodes may be assigned a 3^(rd) classpriority level.

[0096]FIG. 12 is a flowchart showing how a node initials transmission ofdata packets. Before the node starts to transmit a data packet, awaiting/idle time for the transmission of that particular data packetwill be generated. Such a waiting time comprises a random waiting timegenerated by the micro-controller or processor of the node, and a basicwaiting time corresponding to the priority level assigned to it. Awaiting timer is then initialized. While waiting, the node will checkwhether the bus is available/free for transmission. If not, the waitingtimer will be re-initialized, and the checking process is carried outagain. If the bus is found to be available/free for transmission, butthe waiting time is not yet up, the node will keep on checking theavailability of the bus for transmission. If the bus is found to beavailable/free for transmission, and the waiting time is up, the nodewill then start transmission of a data packet. The process will startagain when the node seeks to transmit a second data packet, and so on.It can be seen that, as mentioned above, a node to which a higherpriority level is assigned will have a higher chance of having its datapackets transmitted, than a node to which a lower priority level isassigned.

[0097] The above arrangement of assigning priority levels to the nodesforming the system assists in avoiding collision in the transmission ofdata/signals. However, it is still possible that the respective waitingtime of two or more nodes end at exactly the same time, so that theyseek to transmit their own data/signals at the same time. The methoddiscussed below is then used to prevent collision.

[0098] As shown in FIG. 13, four nodes (A, B, C and D) having the samepriority level and the same total waiting time seek to transmit arespective data packet at the same time. For the purpose of this exampleonly, only the start bit (ST) and first four data bits are shown. Inthis example, node A seeks to transmit data “1111”, node B seeks totransmit data “0111”, node C seeks to transmit data “0010” and node Dseeks to transmit data “0011”. In this connection, the flowcharts inFIGS. 14 and 15 set out the procedure whereby collision is avoided.

[0099] For a better analysis of the process of collision avoidance, letus look back at FIGS. 6 and 7. It can be seen that, in order to have alogic low on the bus, the current mode transmitter of the node must sinka current. On the other hand, in order to have a logic high on the bus,the transmitter must be cut off. This shows that the system is of thenature of a wired-AND logic. In other words, it only requires thetransmitter of one node to sink a current to bring about a logic low onthe bus. However, in order to have a logic high on the bus, all thetransmitters of the nodes connected to the bus/transmission medium haveto be cut off. As the transmitters are cut off when the relevant node isidle, we may also consider that a logic high is being transmitted intothe bus in this situation.

[0100] A first node transmitting a logic high into the bus may beconsidered to hand out the right to control the bus. This first nodethen checks whether a second node(s) is also using the bus by detectingif a logic low is being transmitted into the bus. If there is such asecond node(s), the first node, i.e. the node transmitting a logic highinto the bus, will have to back-off, i.e. the first node will abort itsown transmission, handing over the right to control the bus to thesecond node(s). By way of such an arrangement, the transmission of thelogic low by the second node(s) is in no way affected, thus realizingcollision-free transmission.

[0101] In the case of node A shown in FIG. 13, after initializing thetransmission of a logic-high data bit “1” into the bus (starting fromthe time 1.0T), it checks whether the bus correctly responds (a logichigh). If no such logic high is found in the bus, node A will have toback-off. If, however, a logic high is found in the bus, the node willthen continuously monitor whether this logic high has been transmittedfor its full time duration, which is T in this instance when alogic-high data bit “1” is sought to be transmitted. If the transmissionhas lasted for the fill time duration of T, the node will continue tosend the next bit. If not, the node will have to back off, re-generate awaiting time, and wait for transmission again. In this example, althoughthe node A seeks to transmit a logic-high data bit “1” during the timeperiod 1.5T to 2.0T, as the other three nodes B, C and D are seeking totransmit a logic low, no logic high is present on the bus. The node Ahas to back-off, thus discontinuing the transmission of its data packet.It will then have to wait for a further time period before it can try totransmit again. For the same reason, node B has to back-off when itseeks to transmit the logic high data bit “1” during the time period of2.5T to 3.0T, in view of the fact that the other two nodes C and D areseeking to transmit a logic low.

[0102] While the flowchart in FIG. 14 deals with procedure ofbacking-off when a node is seeking to transmit a logic high data bit “1”(e.g. node A during the time period 1.0T to 2.0T), the flowchart in FIG.15 deals with the procedure of backing-off when a node is seeking totransmit the logic high part of a data bit “0”. As shown in FIG. 13,when the node C seeks to transmit the final data bit “0”, it has totransmit a logic high of a time duration of T/2 to the bus in order tocomplete the whole data bit “0”, during the time period 4.5T to 5.0T.Again, it has to check whether a logic high is present on the bus. Ifnot (as in this case), collision is detected and node C has to back offand discontinue its transmission of the data packet. If, however, alogic high is detected on the bus, the node C has to monitor as towhether the transmission of this logic high has lasted for a timeduration of T/2. If so, it will then continue with the transmission ofthe next bit. If not, the node C will have to back off, re-generate anew waiting time, and wait for transmission again.

[0103] As the network in the present example is a wired-AND logicsystem, we have concentrated our discussion and analysis on the back-offcontrol during the transmission of logic high. The steps for thetransmission of a logic low into the bus by a node are as follows. Thenode seeking to transmit a logic low into the bus first checks thestatus of the bus to ensure that such is available for transmission. Ifa logic high is detected on the bus, the node transmits the logic lowinto the bus for the full period of the logic-low time-width. If,however, no logic high is detected on the bus, the node will stoptransmission and back off.

[0104] As can be seen in FIG. 13, although the four nodes A, B, C, Dseek to transmit a respectively different data packet into the bus atthe same time, at least one node (the node D in this example) cansuccessfully transmit its data packet. To node D, it transmits its datasignals as if no other node is transmitting at the same time.

[0105] We can see from the above analysis that this system constitutes awired-AND logic system, and collision-free communication is realizedthrough back-off control during the transmission of logic high into thebus. It is, however, possible to change the whole system into a wired-ORlogic system by changing the current mode transmitter from a sinkcurrent transmitter to a source current transmitter. This means that apositive pulse will be on the bus provided the source currenttransmitter of at least one node transmits. However, the transmitters inall the nodes have to be cut off together if a negative pulse is to beon the bus, or if the system is to be in the idle state. In such awired-OR system, it is possible to realize collision-free communicationby performing back-off control during the transmission of Logic low intothe bus, in a manner similar to the backing-off during the transmissionof logic high signals into the bus in a wired-AND logic system.

[0106]FIG. 16 is a schematic drawing of a four-node system in which thesituation shown in FIG. 13 occurs, and FIGS. 17A to 24 show the changeof the current/voltage at/across various locations in the system. FIGS.17A to 17D show the waveform of the respective voltage v_(a), v_(b),v_(c) and v_(d) at the micro-controller/processor output (O/P) of eachof the four nodes A, B, C and D over time. As the transmitterconstitutes an inverter in terms of logic, we can see that the waveformsin FIGS. 17A to 17D are opposite to that shown in FIG. 13. It can beseen that, of these four nodes A, B, C and D, only node D cansuccessfully output all the data bits which it seek to transmit.

[0107]FIGS. 18A to 18D show the waveform of the respective sink currenti_(a), i_(b), i_(c) and i_(d) entering each respective node over time.Each sink current (i_(a), i_(b), i_(c), i_(d)) includes a basic current(I_(a), I_(b), I_(c), I_(d)) and a transmitter current (I_(t)). It canbe seen that there is a surge of the sink current (i_(a), i_(b), i_(c),i_(d)) whenever a negative pulse is transmitted into the bus by therelevant node. As the node A 302 a′ cannot successfully transmit thefirst data bit “1”, there is only a surge of the inflow of the sinkcurrent i_(a) from I_(a) to I_(a)+I_(t)when the start bit issuccessfully transmitted, in which I_(a) is the basic system currentflowing into the node A when it is not transmitting. As to the node B302 b′, and as shown in FIG. 18b, as it can only successfully transmitthe first data bit “0”, there is only a corresponding increase incurrent inflow (i_(b)) from I_(b) to I_(b)+I_(t) when the start bit andthe first data bit “0” are transmitted, in which I_(b) is the basicsystem current flowing into the node B when it is not transmitting.FIGS. 18C and 18D show the change of the current i_(c) and i_(d) flowinginto the node C 302 c′and D 302 d′respectively.

[0108]FIGS. 19A to 19D show the waveform of the input (IP) voltage(v_(a), v_(b), v_(c), v_(d)) of the respectivemicro-controller/processor 310 of each of the nodes A, B, C and D. Itcan be seen that all micro-controllers/processors 310 receive the sameseries of electrical pulses, which correspond to the electrical pulsestransmitted by the node D as indicated in FIG. 16, meaning that allthese nodes A, B, C and D receive the data transmitted by the node Donly, and such are the only data that can be transmitted successfullyinto the bus 308.

[0109] The waveform of the total DC current i on the bus over time isshown in FIG. 20. The total DC current i on the bus at any time is, inthis example, the sum total of i_(a), i_(b), i_(c) and i_(d) (see FIGS.18A to 18D) at that time. The maximum value of i is equal to I₀+4I_(t)(assuming that the transmitter current of each of these four nodes isI_(t) and all the nodes are transmitting the start bit simultaneously)in which I₀ is the total current flowing through the system when no nodeis transmitting, and is the sum total of I_(a), I_(b), I_(c) and I_(d)in this example. As to the electric current i_(l) flowing through theinductor 322 at any given point of time, such is shown in FIG. 21. Itcan be seen that this current i_(l) is always no less than I₀ and nomore than I₀+I_(t), and varies in accordance with the electric voltagev_(p) across the bi-directional clamp 324 (to be discussed below).

[0110] As to the current i_(p) flowing through the bi-directionalvoltage clamp 324, such is shown in FIG. 22. Its maximum value is4I_(t), when all four nodes A 302 a′, B 302 b′, C 302 c′ and D 302 d′are transmitting the start bit of their respective data packet. It canbe seen that i_(p) may sometimes be of a negative value. Such means thatthe current i_(p) is flowing in a direction opposite to that as shown inFIG. 16, and thus through the upper pair of diodes in the voltage clamp324. As to the voltage v_(p) across the bi-directional voltage clamp324, such is shown in FIG. 23, and it fluctuates between a positive“clamp voltage” and a negative “clamp voltage”. As to the voltage v inthe bus 308, such is shown in FIG. 24, as fluctuating between V₀+ClampVoltage and V₀−Clamp Voltage, in which V₀ is the electric potential ofthe DC power source 320.

[0111] We can therefore see that, when the current mode transmitter 304transmits, an AC component of an amplitude of ±Clamp Voltage issuperimposed on the DC voltage, thus realizing the conversion ofelectric current into electric voltage. In addition, the amplitude ofthe electric voltage does not depend on the value of the electriccurrent in the transmitter, so that the amplitude of the electricvoltage is not affected even when several nodes are transmitting at thesame time.

[0112] The above analysis is made on the basis of the basic structure ofthe system 100 shown in FIG. 3. Stated simply, the system 100 in FIG. 3includes a bus 104 with two wires, in which the bus 104 carries theelectric power, current signals and voltage signals. The bus 104 is alsopolarity insensitive to the nodes 102.

[0113] However, there can be variations in actual application. One may,for example, separate the power path in the bus, or separate the currentpath from the voltage path. FIG. 25 shows an example of such anembodiment. FIG. 25 shows a system 400 with three nodes 402inter-connected with one another, and with a current/voltage converter404 via a bus 406. Each of the nodes 402 is a transceiver including acurrent mode transmitter 408 and a voltage mode receiver 410.

[0114] The current/voltage converter 404 includes a current terminal 412and a voltage terminal 414. The current terminal 412 of thecurrent/voltage converter 404 is connected with the current modetransmitters 408 of the nodes 402 on the bus 406 to form a currenttransmission path (Tx) of the bus 406. On the other hand, the voltageterminal 414 is connected with the voltage mode receiver 410 of thenodes 402 on the bus 406 to form a voltage receiving path (Rx) of thebus 406. The nodes/transceivers 402 on the bus 406 obtain the necessaryelectric power from a DC power source 416 through a V+ path of the bus406. With the inclusion of a Ground path (Gnd), the bus 406 includes atotal of four wires.

[0115] The current/voltage converter 404 may be realized by a currentloop receiver (e.g. HCPL-4200 of Hewlett Packard). As to applicationmodule and current mode transmitter, one may adopt the structuresdiscussed above. As it is not necessary for the voltage mode receivers410 to isolate the DC power potential from the bus, no input capacitoris required.

[0116] As discussed above, one of the major advantages of separating thepower path from the signal path is that the current controller 108 shownin FIG. 3 is no longer required. On the other hand, one of its majordisadvantages is that, with the increase in the number of wires in thebus 406, not only is it not possible to realize polarity insensitivity,the chance of mis-wiring will also increase.

[0117] Apart from the increase in the number of wires in the bus 406,there is not much difference in the nature of the system 400 with thatas shown in FIG. 3. This system 400 also supports the simultaneoustransmission of signals by more than one node 402, and is still areal-time-response and wired-AND logic system. The priority setting andcollision-free communication method discussed above can also beimplemented in this system 400.

[0118] It is clear from the foregoing discussions that a mixed modemultidrop network system according to the present invention possessesthe following advantages and characteristics:

[0119] A. Such a network system successfully combines the advantages ofvoltage mode networks and current loop systems. As the receivers in sucha network system have a high impedance, and the bus in the networkexhibits a low impedance, DC can flow through the system almost withoutresistance (which enhances the operation of a link power system), theinterference of AC of 50/60 Hz can be effectively filtered. Suchcharacteristics are particularly important for a control system. Thus,in the field of control, the use of a mixed mode network according tothe present invention is more advantageous.

[0120] B. Such is a link power network system, allowing the simultaneousdistribution of power and signals/data along the same twisted pair wire.Such allows easy installation by the users, and enhances the integrationof the nodes with the network. In such a system, electric power iscoupled from the bus using a constant current source. Such a couplingmethod is of a high impedance, thus causing minimal effect on thesignals/data in the bus. In addition, the transceivers in such a systemare connected directly to the bus, thus avoiding the use oftransformers. Such will reduce the size and cost of the system, and canenhance its reliability.

[0121] C. Such a system adopts the simplest and most common singleunshielded twisted pair (UTP) wire as the bus/transmission medium. Asthere are only two wires and they are not of any polarity (because ofthe bridge rectifier 230, 232 shown in FIG. 4 and discussed above), thepossibility of mis-wiring does not exist in this system, and such allowsconvenient installation and wiring.

[0122] D. Such is a decentralized network system in which each node canfunction independently. It is thus relatively easy to expand the system.In addition, the present network system is a zero dominion system (i.e.a non-master/slave or non-announcer/listener structure) in which eachnode may be a master/announcer, and may also be a slave/listener. Eachnode listens to the bus all the time and can, according to its needs,transmit signals/data into the bus.

[0123] E. Such a network system adopts a random access control method,in which any node is allowed to transmit when the bus/transmissionmedium is free (subject to the control of priority setting). Polling isnot required in the present invention. Such enhances the efficiency ofcommunication within the system, and the versatility of the nodes.

[0124] F. In order to achieve the collision-free communication in thepresent invention, the present system possesses a number ofcharacteristics:

[0125] (a) an appropriate network structure—the network structure in thepresent system ensures that even in case of multiple simultaneousaccess, the digital signals in the transmission media will still presenta predetermined logic state, i.e. no uncertain logic state will existand all logic states can be effectively identified;

[0126] (b) an access control mechanism of immediate response—thereceiver and transmitter in each of the nodes are controlled directly bya micro-controller or processor, which can ascertain the state of thebus on a real-time basis. When a node detects a collision, it canback-off in time; and

[0127] (c) appropriate data format and communication protocol.

[0128] G. In such a system, even if more than one node transmitdifferent data packets at the same time, at least one node willsuccessfully transmit its whole data packet, thus realizingcollision-free transmission.

[0129] H. In such a system, a number of different priorities areestablished. During a period of busy communication, a node to which ahigher priority is assigned will have a higher chance of being able totransmit its data/data packets.

[0130] I. Such a system is suitable for use in carrying out sensing,communication and control functions.

What is claimed is:
 1. A digital data communication network systemincluding a power supply means and at least two nodes, wherein saidpower supply means and said nodes are connected to one another via atransmission media whereby digital signals/data are transmissiblebetween said nodes, wherein said power supply means supplies electricpower to said nodes, and wherein at least one of said nodes includes acurrent mode transmitter and at least one of said nodes includes avoltage mode receiver.
 2. The system according to claim 1 wherein atleast one of said plurality of nodes includes a current mode transmitterand a voltage mode receiver.
 3. The system according to claim 2 whereina plurality of said nodes include a current mode transmitter and avoltage mode receiver.
 4. The system according to claim 3 wherein eachof said nodes includes a current mode transmitter and a voltage modereceiver.
 5. The system according to claim 1 wherein said transmissionmedia is a unshielded twisted pair wire.
 6. The system according toclaim 1 wherein said system includes pulse generating means throughwhich electric current from said power supply means passes to induce avoltage pulse.
 7. The system according to claim 6 wherein said pulsegenerating means comprises a current to voltage converter means.
 8. Thesystem according to claim 6 wherein said pulse generating means isconnected in parallel to a current controller.
 9. The system accordingto claim 1 wherein said power supply means comprises a DC power source.10. The system according to claim 1 wherein said voltage mode receiverincludes a capacitor and an inverter means.
 11. A digital datacommunication system for delivering digital signals from a current modetransmitter to a voltage mode receiver, said system including: anelectrically conductive cable coupling said transmitter and saidreceiver with each other, thereby providing a digital datacommunications path; DC power supply means for producing apre-determined electric potential, said power supply means having afirst voltage terminal and a second voltage terminal; current controlmeans coupling said first voltage terminal of said power supply means tosaid cable for providing a first electric current path, said firstelectric current path operating as a low impedance path for DC current;voltage control means connected in parallel with said current controlmeans for controlling the voltage amplitude across said current controlmeans, and for providing a second electrical path for transient electriccurrent; connecting means coupling said second voltage terminal of saidpower supply means to said cable to provide a power distribution path;wherein said current mode transmitter is coupled to said cable forimplementing a current loop, wherein said transmitter produces currentpulses in said current loop to perform a current mode digital datatransmission; and wherein said voltage mode receiver is coupled to saidcable for receiving voltage pulses on said cable produced by saidvoltage control means to perform a voltage mode digital data reception.12. The system according to claim 11 wherein said conductive cablecomprises a single twisted pair wire.
 13. The system according to claim11 wherein said current control means comprises a cored inductor. 14.The system according to claim 11 wherein said voltage control meanscomprises a bi-directional voltage clamp.
 15. The system according toclaim 11 wherein said pre-determined electric potential is substantially24 volts.
 16. The system according to claim 11 wherein each of saidcurrent mode transmitter and said voltage mode receiver includes: abridge rectifier having two terminals coupled to said cable forproviding a non-polarity interface with said cable, said rectifierfurther including a +terminal and a −terminal; a constant current sourcehaving a first current terminal and a second current terminal, whereinsaid first current terminal is coupled to said +terminal; and a zenerdiode coupling said second current terminal of said constant currentsource to said −terminal of said rectifier to provide a power supply tosaid transmitter and said receiver.
 17. The system of claim 16 whereinsaid transmitter further includes: a transistor with a collector coupledto said +terminal of said rectifier, a base for inputting data to betransmitted into said transistor, and an emitter; and a resistorcoupling said emitter of said transistor and said −terminal of saidrectifier for implementing a transmission output current loop.
 18. Thesystem according to claim 16 wherein said receiver includes an inputcapacitor for isolating the direct current potential on said +terminalof said bridge rectifier.
 19. A digital data communication networksystem for distributing power and for providing signal passingcapabilities through a bus, said network including: a plurality of nodeseach including a mixed mode data bus transceiver for generating electriccurrent pulses and receiving electric voltage pulses; an electricallyconductive cable coupling said nodes with one another to provide a pathfor power delivery and data communications; a DC power supply means forproducing a pre-determined electric potential, said power supply meanshaving a first voltage terminal and a second voltage terminal; currentcontrol means coupling said first voltage terminal of said power supplymeans to said cable for providing a first DC current low impedance path;voltage control means connected in parallel with said current controlmeans for controlling the voltage amplitude across said current controlmeans and providing a second current path for transient current; andconnection means coupling said second voltage terminal of said powersupply means to said conductive cable to provide a power distributionpath.
 20. The system according to claim 19 wherein said conductive cablecomprises a single twisted pair wire.
 21. The system according to claim19 wherein said current control means includes a cored inductor.
 22. Thesystem according to claim 19 wherein said voltage control means includesa bi-directional voltage clamp.
 23. The system according to claim 19wherein said pre-determined electric potential is substantially 24volts.
 24. The system according to claim 19 wherein the frequency ofsaid pulses is substantially between 5 kHz to 50 kHz.
 25. The systemaccording to claim 19 wherein each of said nodes includes amicro-controller/processor.
 26. The system according to claim 19 whereinsaid data bus transceiver includes: a bridge rectifier having a firstand a second connection terminal for providing a non-polarity interfacewith said bus, said rectifier further including a +terminal and a−terminal; a current mode transmitter coupled to said +terminal and said−terminal of said rectifier for implementing a current loop forproducing electric current pulses to said bus to perform a current modedata transmission; a voltage mode receiver coupled to said +terminal andsaid −terminal of said rectifier, said receiver receiving voltage pulseson said bus to perform a voltage mode data reception; and currentcoupling means coupled to said +terminal and said −terminal of saidrectifier for providing a regulated direct current supply to saidtransceiver.
 27. The system according to claim 26 wherein saidtransceiver includes a transmitter including: a transistor with acollector coupled to said +terminal of said rectifier, a base forinputting data to be transmitted to the transistor, and an emitter; anda resistor having a first terminal coupled to said emitter of saidtransistor and a second terminal coupled to said −terminal of saidrectifier.
 28. The system according to claim 26 wherein said transceiverincludes a receiver including: a transistor with a collector coupled tosaid −terminal of said rectifier through a resistor for outputting thedata received from said bus, and a base; and a capacitor coupling saidbase of said transistor with said +terminal of said rectifier through aresistor for providing an AC path to said bus.
 29. The system accordingto claim 26 wherein the current coupling means includes: a constantcurrent source having a first terminal and a second terminal, whereinsaid first terminal is coupled to said +terminal of said rectifier forsourcing a constant current; and a zener diode coupling said secondterminal of said constant current source and said −terminal of saidrectifier for providing a regulated DC voltage source.
 30. A transceiveradapted to transmit and receive digital signals on a data bus whichdelivers direct current power and digital data simultaneously, saidtransceiver including: a bridge rectifier having two connectionterminals adapted to provide a non-polarity interface with said bus,said rectifier further including a +terminal and a −terminal; a currentmode transmitter coupled to said +terminal and said −terminal of saidrectifier for implementing a current loop adapted to produce electriccurrent pulses to said data bus to perform current mode datatransmission; a voltage mode receiver coupled to said +terminal and said−terminal of said rectifier, said receiver being adapted to receiveelectric voltage pulses on said data bus to perform voltage mode datareception; and a current coupling means coupled to said +terminal andsaid −terminal of said rectifier, said current coupling means beingadapted to provide a regulated direct current supply to said transmitterand said receiver and other means in said transceiver.
 31. Thetransceiver according to claim 30 wherein said transmitter includes: atransistor with a collector coupled to said +terminal of said rectifierand a base for inputting the data to be transmitted, and an emitter; anda resistor having a first terminal coupled to said emitter of saidtransistor and a second terminal coupled to said −terminal of saidrectifier.
 32. The transceiver according to claim 30 wherein saidreceiver includes: a transistor with a collector coupled to said−terminal of said rectifier through a resistor for outputting the datareceived, and a base; and a capacitor coupled with said base of saidtransistor and said +terminal of said rectifier through a resistor, andbeing adapted to provide an AC path to said bus.
 33. The transceiveraccording to claim 30 wherein said current coupling means includes: aconstant current source having a first terminal and a second terminal,wherein said first terminal is coupled with said +terminal of saidrectifier and adapted for sourcing a constant current; and a zener diodecoupled with said second terminal of said constant current source andsaid −terminal of said rectifier, and adapted to provide a regulated DCelectric voltage.
 34. The transceiver according to claim 33 wherein theworking voltage of said zener diode in said coupling means issubstantially 5 volts.
 35. The transceiver according to claim 30 whereinthe pre-determined DC potential of said power is substantially 24 volts.36. The transceiver according to claim 30 wherein the range of frequencyof said current and voltage pulses in said transceiver is 5-50 kHz. 37.The transceiver according to claim 30 wherein said other means includesa micro-controller/processor.
 38. A method of communication in a mixedmode communication and control network system, wherein said systemincludes at least a first node, a second node, a power supply means, andcurrent to voltage converter means connected with one another via a bus,comprising the steps of: (a) generating at least a first electric pulseby said first node; (b) transmitting said first electric pulse to saidpower supply means in the form of an electric current; (c) causing afirst electric current from said power supply means to pass through saidcurrent to voltage converter means to induce at least a second electricpulse; and (d) transmitting said second electric pulse into said bus.39. The method according to claim 38 wherein said first electric pulseis generated by a micro-controller/processor.
 40. The method accordingto claim 39 wherein said first electric pulse is generated by saidmicro-controller/processor upon a change in state of an applicationmodule.
 41. The method according to claim 38 wherein said current tovoltage converter means is connected in parallel with a current controlmeans.
 42. The method according to claim 38 wherein a second electriccurrent passes through said current control means when said firstelectric current passes through said current to voltage converter means.43. The method according to claim 42 wherein the magnitude of saidsecond electric current passing through said current control meansvaries at least in part in accordance with the period of time duringwhich said second electric current passes through said current-controlmeans.
 44. The method according to claim 42 wherein the magnitude ofsaid second electric current passing through said current control meansdepends at least in part on the electric voltage across said currentcontrol means.
 45. The method according to claim 38 wherein the polarityof said first electric pulse is opposite to the polarity of the secondelectric pulse.
 46. The method according to claim 38 wherein said secondelectric pulse is received by said second node.
 47. The method accordingto claim 46 wherein said second node includes a voltage mode receiverfor receiving said second electric pulse.
 48. The method according toclaim 47 wherein said voltage mode receiver of said second node includesinverter means for inverting the polarity of said second electric pulse.49. The method according to claim 48 wherein said inverted secondelectric pulse is inputted into a micro-controller/processor of saidsecond node.
 50. A method for medium access control in a mixed modecommunication and control network system, wherein said system includesat least a first node and a second node each being adapted to transmitsignals into a bus via which said nodes are connected with each other,including the steps of: (a) establishing a plurality of priority levelseach with a corresponding different range of waiting time; (b) assigningone of said plurality of priority levels to each of said nodes; (c) saidfirst node generating a waiting time on the basis of the priority levelassigned thereto; (d) said first node checking whether said bus is freefor transmission; (e) said first node checking whether said waiting timehas expired; (f) repeating steps (d) and (e) until the waiting time hasexpired; and (g) commencing transmission of a first data packet by saidfirst node if said bus is free for transmission.
 51. The methodaccording to claim 50 wherein seven priority levels are established. 52.The method according to claim 50 wherein said period of waiting timecomprises a pre-determined basic time component and a random timecomponent.
 53. The method according to claim 52 wherein the period ofthe basic time component of the waiting time of each priority level isdifferent.
 54. The method according to claim 52 wherein the period ofthe random time component of the waiting time of each priority level isset within a predetermined range.
 55. The method according to claim 54wherein the pre-determined range of period of the random time componentof the waiting time of the priority levels is the same.
 56. The methodaccording to claim 52 wherein said random time component of the waitingtime is generated by a micro-controller/processor of said first node.57. The method according to claim 50 wherein said first nodere-initialize the waiting time and starts from step (c) again if saidbus is not free for transmission or not free for the full period of thewaiting time.
 58. A method of transmitting data in a mixed modecommunication and control network system, wherein said system includesat least a first node and a second node each being adapted to transmitpulses into a bus via which said nodes are connected with each other,including the steps of: (a) said first node causing a pulse of a firstpolarity to be transmitted into said bus; (b) said first node checkingwhether a pulse of said first polarity appears on said bus; and (c)finishing sending said pulse of said first polarity into said bus forthe full period of pulse time-width if a pulse of said first polarity isdetected on said bus in step (b).
 59. The method according to claim 58wherein said first node stops sending said pulse of said first polarityinto said bus if no pulse of said first polarity is detected on said busin step (b).
 60. The method according to claim 58 wherein said firstpolarity is positive.
 61. A method of transmitting at least one datapacket for providing a collision-free communications in a mixed-modemulti-drop random access digital control network, wherein said networkincludes at least a first node and a second node each being adapted totransmit and receive data packets through a bus via which said nodes areconnected with each other and constituting a wired-AND logic, whereinsaid data packet includes at least a logic high and a logic low to betransmitted into said bus, said method including the steps of: (a) whensaid first node seeks to transmit said logic low into said bus, saidfirst node: (1) checks logic state from said bus; (2) starts to transmitsaid logic low into said bus if said bus presents logic high in step (1)above; (3) completes transmitting said logic low into said bus for thefull period of the time-width of the said logic low; and (b) when saidfirst node seeks to transmit said logic high into said bus, said firstnode: (1) starts to transmit said logic high into said bus; (2) checkslogic state from said bus; (3) checks whether a pre-determined waitingtime is up; and (4) repeats steps (b)(2) and (b)(3) until said firstnode completes transmission of said logic high into said bus for thefull period of the time-width of said logic high if said bus keep onpresenting logic high in step (b)(2).
 62. The method according to claim61 wherein said first node stops transmission of said data packet andbacks off if said bus does not present logic high in step (a)(1). 63.The method according to claim 61 wherein said first node stopstransmission of said data packet and backs off if said bus does notpresent logic high in step (b)(2) for the full period of the time-widthof said logic high.
 64. The method according to claim 61 wherein allsaid steps are carried out by a micro-controller/processor of said firstnode.
 65. A method of transmitting at least one data packet forproviding a collision-free communications in a mixed-mode multi-droprandom access digital control network, wherein said network includes atleast a first node and a second node each being adapted to transmit andreceive data packets through a bus via which said nodes are connectedwith each other and constituting a wired-OR logic, wherein said datapacket includes at least a logic high and a logic low to be transmittedinto said bus, said method including the steps of: (a) when said firstnode seeks to transmit said logic high into said bus, said first node:(1) checks logic state from said bus; (2) starts to transmit said logichigh into said bus if said bus presents logic low in step (1) above; (3)completes transmitting said logic high into said bus for the full periodof the time-width of the said logic high; and (b) when said first nodeseeks to transmit said logic low into said bus, said first node: (1)starts to transmit said logic low into said bus; (2) checks logic statefrom said bus; (3) checks whether a pre-determined waiting time is up;and (4) repeats steps (b)(2) and (b)(3) until said first node completestransmission of said logic low into said bus for the full period of thetime-width of said logic low if said bus keep on presenting logic low instep (b)(2).
 66. The method according to claim 65 wherein said firstnode stops transmission of said data packet and backs off if said busdoes not present logic low in step (a)(1).
 67. The method according toclaim 65 wherein said first node stops transmission of said data packetand backs off if said bus does not present logic low in step (b)(2) forthe full period of the time-width of said logic low.
 68. The methodaccording to claim 65 wherein all said steps are carried out by amicro-controller/processor of said first node.
 69. A transceiver adaptedto transmit and receive digital signals/data via a mixed mode bus whichdelivers direct current power and digital data simultaneously, saidtransceiver including current mode transmitter means for implementing acurrent loop adapted to produce electric current pulses to said bus toperform a current mode data transmission, and voltage mode receivermeans for receiving electric voltage pulses on said bus to performvoltage mode data reception.
 70. The transceiver according to claim 69wherein said transceiver further includes bridge rectifier means forproviding a polarity insensitive interface with said bus.
 71. Thetransceiver according to claim 69 wherein said transceiver furtherincludes current coupling means for providing a regulated direct currentsource.
 72. The transceiver according to claim 69 wherein saidtransmitter means comprises a sink current loop driver.
 73. Thetransceiver according to claim 69 wherein said receiver means includesan input capacitor and an inverter means.
 74. The transceiver accordingto claim 69 wherein said transceiver further includes amicro-controller/processor.
 75. The transceiver according to claim 69wherein the range of frequency of said current and voltage pulses is5-50 kHz.
 76. The transceiver according to claim 69 wherein thepre-determined DC potential of said power is substantially 24 volts. 77.The transceiver according to claim 69 wherein said transceiver furtherincludes a sensor module.
 78. The transceiver according to claim 69wherein said transceiver further includes a control module.
 79. Thetransceiver according to claim 69 wherein said transceiver furtherincludes a priority setting module.
 80. The transceiver according toclaim 71 wherein said current coupling means comprises a constantcurrent source connected in series with a zener diode.